This invention relates to programmable integrated circuits and more particularly, to programmable integrated circuits having embedded blocks that are double clocked.
A programmable integrated circuit such as a programmable logic device (PLD) typically includes programmable logic blocks, random access memory (RAM) blocks, and digital signal processing (DSP) blocks. The programmable logic blocks contain programmable memory elements that are loaded with configuration data, which configure the programmable logic blocks to implement a custom user function.
Conventionally, the different types of blocks on a programmable logic device operate using the same clock frequency (i.e., the programmable logic blocks, the RAM blocks, and the DSP blocks are clocked at the same rate). In an effort to improve the overall performance of the programmable logic device, techniques have been developed that involve use of a double data rate DSP block. For example, a DSP block on the device may be operated at 500 MHz while an associated programmable soft logic is operated at only 250 MHz. Such schemes, however, require redesigning the DSP block to operate at two times the frequency relative to the rest of the system, which can be costly and challenging to implement. Moreover, routing connections between the 500 MHz DSP block and the 250 MHz soft logic are oftentimes complex and introduce heavy routing stress, which can potentially reduce any performance gain provided by the faster DSP block.
It is within this context that the embodiments herein arise.